1. Field of Invention
The present invention relates to an interface connecting method and apparatus for a personal computer system. More particularly, the present invention relates to an interface connecting method and apparatus for a low pin count bus in a personal computer system.
2. Description of Related Art
A basic input/output system (BIOS, hereinafter) is a quite traditional yet very important part in technologies of a personal computer (PC, hereinafter) system. BIOS is the first program that a PC system executes at start up, and many lowest level system functions are provided by the BIOS as well. Hence, a PC system cannot even start up without the BIOS.
A block diagram of BIOS device in a traditional PC system is shown in FIG. 1. A central processing unit (CPU, hereinafter) 101 is connected to a north bridge integrated circuit (IC, hereinafter) 104 via a host bus 102. Next, the north bridge IC 104 is connected to a group of devices including the host bus 102, an accelerated graphic port (AGP, hereinafter) 103, a memory 105 and a peripheral control interface (PCI, hereinafter) bus 106. The PCI bus 106 is connected to PCI expansion slots 107 and a south bridge IC 108. The south bridge IC 108 is connected to a group of devices including the PCI bus 106, an industrial drive electronics (IDE, hereinafter) interface hard disk drive 109 and an industrial standard architecture (ISA, hereinafter) bus 110. Lastly, the ISA bus 110 is connected to a group of devices including the south bridge IC 108, a BIOS device 111, and a super input/output (I/O, hereinafter) card 112. Wherein the super I/O card 112 is for connecting peripherals who support traditional interface only and whose interface transmitting speed is slower, such as a modem, a printer, a keyboard, a mouse, and a joystick.
A standard ISA bus requires 49 pins with 8 MHz clock frequency according to the architecture described above. However, the strong competition in PC industry nowadays drives for a lower cost continuously. Hence, the ISA bus is gradually replaced by a low pin count (LPC, hereinafter) bus that adopts fewer pins and is lower cost. A LPC bus needs only 9 pins, yet its clock frequency is increased to 33 MHz to maintain the transmission bandwidth via the fewer pins.
However, using the LPC bus brings a problem of connecting the BIOS device with traditional ISA interface to a PC system with a LPC bus. A solution is to connect via a super I/O card as shown in FIG. 2. Wherein, the original ISA bus 110 is replaced by a LPC bus 201, and a BIOS device 111 with ISA interface is connected to the LPC bus 201 via an ISA bus 203 and a super I/O card 202 which supports the LPC bus.
In most cases, a flash memory is used for storing the BIOS program, while a traditional flash memory is using a parallel interface. Accordingly, the block diagram of a super I/O card is shown in FIG. 3. The super I/O card 202 comprises a LPC bus decoder 301, a register mode controller 302, and a bus converter 303. Wherein, the LPC bus decoder 301 reads an instruction from the LPC bus 201, converts the instruction to a format which is easier for processing, transmits the converted instruction to the register mode controller 302 and the bus converter 303, and further transmits the output data from a parallel flash memory 304 to the LPC bus 201. The register mode controller 302 controls assorted functions of the parallel flash memory 304 and the bus converter 303 outputs the decoded instructions to the ISA bus 203 allowing the parallel flash memory 304 to receive them. Meanwhile, the bus converter receives the data outputted from the parallel flash memory 304 as well and transmits the output data back to the LPC bus decoder 301.
The detailed functions of the bus converter 303 are shown in FIG. 4. According to time sequence starting from left side, the signals of instruction on the LPC bus 201 comprises a start signal 401, a command field 402, an address field 403, a data field 404 (only presents in a write instruction), a wait time 405 for waiting the parallel flash memory 304 to execute the instruction and feedback a result, an output data 406 (only presents upon execution of a read instruction), and a terminate signal 407.
According to operations of the bus converter 303, the command field 402, the address field 403, and the data field 404 of a LPC bus instruction are first fetched and stored in a latch 408. Next, those latched signals are converted to an acceptable format of the parallel flash memory 304 by a command decoder 409, an address compare multiplexer 410, and a data compare multiplexer 411 respectively. Those converted signals are outputted to the parallel flash memory 304 via a memory signal converter 412. When a read instruction is executed, the data outputted from the parallel flash memory 304 is transmitted back to the LPC bus 201 to be the output data 406.
The signals appeared on the LPC bus 201 and their correlative timings when a read or write command is executed by the parallel flash memory 304 are shown in FIG. 5. The upper part of the LPC bus 201 illustrates signals of instruction when executing a read command, starting with a start signal 401, a command field 402, an address field 403, a terminate signal 407, a wait time 405, a synchronous signal 501, a output data 406, and another terminate signal 407. The lower part of the LPC bus 201 illustrates signals of instruction when executing a write command, starting with a start signal 401, a command field 402, an address field 403, a data field 404, a terminate signal 407, a wait time 405, a synchronous signal 501, and another terminate signal 407.
According to FIG. 5, a wait time 405 is always present for waiting the parallel flash memory 304 finishing execution after an instruction is transmitted, regardless of read instruction or write instruction. According to the comparison of the wait time 405 with the LPC bus clock signal 502 and with the ISA bus clock signal 503, the duration of the wait time 405 is equivalent to 4.5 ISA bus clock cycles or 18 LPC bus clock cycles approximately.
For further cost down, a serial flash memory with fewer pins is preferred for storing BIOS. While neither a prior art nor an existing apparatus, e.g. a super I/O card, is available currently for connecting a serial flash memory to the LPC bus. Therefore, a new technology is needed for connecting LPC bus and serial flash memory, in order to further reduce the cost of a PC system.